1 of 8 features ? 10 years minimum data retention in the absence of external power ? data is automatically protected during power loss ? directly replaces 2k x 8 volatile static ram or eeprom ? unlimited write cycles ? low - power cmos ? jedec standard 24 - pin dip package ? read and write access times of 100 ns ? lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ? full 10% v cc operating range (ds1220ad) ? optional 5% v cc operating range (ds1220a b) ? optional industrial temperature range of - 40c to +85c, designated ind pin assignment 24- pin encapsulated package 720- mil extended pin description a0 -a10 - address inputs dq0 - dq7 - data in/data out ce - chip enable we - write enable oe - output enable v cc - power (+5v) gnd - ground description the ds1220ab and ds1220ad 16k nonvolatile srams are 16,384 - bit, fully static, nonvolatile srams organized as 2048 words by 8 bits. each nv sram has a self - contained lithium energy source and control circuitry which constantly monitors v cc for an out - of - tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on an d wr ite protection is unconditionally enabled to prevent data corruption. the nv srams can be used in place of e xisting 2k x 8 srams directly conforming to the popular bytewide 24 - pin dip standard. the devices also match the pinout of the 2716 eprom and the 2816 eeprom, allowing direct substitution while enhan cing performance. there is no limit on the number of write cycles that can be executed an d no additional support circuitry is required for microprocessor interfacing. ds1220ab/ad 16k nonvolatile sram 19 - 5580; rev 10/10 www.maxim - ic.com 14 vcc we 1 2 3 4 5 6 7 8 9 10 11 12 13 24 15 23 22 21 20 19 18 17 16 a7 a5 a3 a2 a1 a0 d q0 dq1 gnd dq2 a6 a4 a8 a9 oe a10 ce dq7 dq6 dq5 dq3 dq4 downloaded from: http:///
ds1220ab/ad 2 of 8 read mode the ds1220ab and ds1220ad e xecute a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (output enable) are active (low). the unique address specified by the 11 address inputs (a0 - a10) defines which of the 2048 bytes of data is to be accessed. valid data wil l be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that the ce and oe access times are also satisfied. if ce and oe access times are not satisfied, then data access must be measured from the later - occurring signal and the limiting parameter is either t co for ce or t oe for oe rather than address access. write mode the ds1220ab and ds1220ad execute a write cycle whenever the we and ce signals are active (low) after address inputs are stable. the latter occu rring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output d rivers are enabled ( ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the ds1220ab provides full functional capability for v cc greater than 4.75 volts and write protects by 4.5v. the ds1220ad provides full functional capability for v cc greater than 4.5 volts and write protects by 4.25v. data is maintained in the absence of v cc without any additional support circuitry. the nonvolatile static rams constantly monitor v cc . should the supply voltage decay, the nv srams automatically write protect themselves, all inputs become dont care, and all outputs become high impedance. as v cc falls below approxima tely 3.0 volts, a power switching circuit connects the lithium energy source to ram to retain data. during power - up, when v cc rises above approximately 3.0 volts, the power switching circuit connects external v cc to ram and disconnects the lithium energy s ource. normal ram operation can resume after v cc exceeds 4.75 volts for the ds1220ab and 4.5 volts for the ds1220ad. freshness seal each ds1220 device is shipped from dallas semiconductor with its lit hium energy source disconnected, guaranteeing full ener gy capacity. when v cc is first applied at a level of greater than v tp , the lithium energy source is enabled for battery backup operation. downloaded from: http:///
ds1220ab/ad 3 of 8 absolute maximum ratings voltage on any pin relative to ground - 0.3v to +6.0v operating temperature range commercial: 0c to +70c industrial: - 40c to +85c storage temperature - 40c to +85c lead tem perature (soldering, 10 s) +260c note: edip is wave or hand soldered only . this is a stress rating only and functional operation of the device at these or any other condit ions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended pe riods of time may affect reliabil ity. recommended dc opera ting conditions (t a : see note 10) parameter symbol min typ max units notes ds1220ab power supply voltage v cc 4.75 5.0 5.25 v ds1220ad power supply voltage v cc 4.50 5.0 5.50 v logic 1 v ih 2.2 v cc v logic 0 v il 0.0 +0.8 v dc electrical characteristics (t a : see not e 10) (v cc = 5v 5% for ds1220ab) (v cc = 5v 10% for ds1220ad) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 a i/o leakage current ce v ih v cc i io -1.0 +1.0 a output current @ 2.4v i oh -1.0 ma output current @ 0.4v i ol 2.0 ma standby current ce = 2.2v i ccs1 5.0 10.0 ma standby current ce = v cc -0.5v i ccs2 3.0 5.0 ma operating current (commercial ) i cc01 75 ma operating current (industrial) i cco1 85 ma write protection voltage (ds1220ab) v tp 4.5 4.62 4.75 v write protection voltage (ds1220ad) v tp 4.25 4.37 4.5 v capacitance (t a = + 25c) parameter symbol min typ max units not es input capacitance c in 5 10 pf input/output capacitance c i/o 5 12 pf downloaded from: http:///
ds1220ab/ad 4 of 8 ac electrical characteristics (t a : see note 10) (v cc = 5.0v 5% for ds1220ab) (v cc = 5.0v 10% for ds1220ad) parameter symbol ds1220ab-100 ds1220ad-100 units notes min max read cycle time t rc 100 ns access time t acc 100 ns oe to output valid t oe 50 ns ce to output valid t co 100 ns oe or ce to output active t coe 5 ns 5 output high z from deselection t od 35 ns 5 output hold from address change t oh 5 ns write cycle time t wc 100 ns write pulse width t wp 75 ns 3 address setup time t aw 0 ns write recovery time t wr1 t wr2 0 10 ns ns 12 13 output high from we t odw 35 ns 5 output active from we t oew 5 ns 4 data setup time t ds 40 ns 4 data hold time t dh1 t dh2 0 10 ns ns 12 13 downloaded from: http:///
ds1220ab/ad 5 of 8 read cycle see note 1 write cycle 1 see notes 2, 3, 4, 6, 7, 8 and 12 write cycle 2 see notes 2, 3, 4, 6, 7, 8 and 13 downloaded from: http:///
ds1220ab/ad 6 of 8 power - down/power - up condition see note 11 power - down/power - up timing (t a : see note 10) parameter symbol min typ max units note s v cc fail detect to ce and we inactive t pd 1.5 s 11 v cc slew from v tp to 0v t f 300 s v cc slew from 0v to v tp t r 300 s v cc valid to ce and we inactive t pu 2 ms v cc valid to end of write protection t rec 125 ms (t a = + 25c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstances are negative undershoots, of any amplitu de, allowed when dev ice is in the battery backup mode. notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high - impedance state. 3. t wp is specified as th e logical and of ce and we . t wp is measured from the latter of ce or ce going low to the earlier of ce or we going high. 4. t ds is mea sured from the earlier of ce or we going high. 5. these parameters are sampled with a 5 pf load and are not 100% tested. 6. if the ce low transition occurs simultaneously with or later than the we low transition, the output buffers remain in a high - impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high - impedance state during this period. downloaded from: http:///
ds1220ab/ad 7 of 8 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high - imp edance state during this period. 9. each ds1220ab and each ds1220ad has a built - in switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. this parameter is guaranteed by de sign and is not 100% tested. 10. all ac and dc electrical characteristics are valid over the full operatin g temperature range. for commercial products, this range is 0c to 70c. for industrial produc ts (ind), this range is - 40c to +85c. 11. in a power down condition the voltage on any pin may not exceed the voltage o n v cc . 12. t wr1 , t dh1 are measured from we going high. 13. t wr2 , t dh2 are measured from ce go ing high. 14. ds1220 modules are recognized by underwriters laborator ies (u l ) under file e99151. dc test conditions outputs open cycle = 200ns for operating current all voltages are referenced to ground ac test conditions output load: 100 pf + 1ttl gate input pulse levels: 0 - 3.0v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5ns ordering information part temp range supply tolerance pin - package ds1220ab-100+ 0c to +70c 5v 5% 24 720 edip DS1220AB-100IND+ - 40c to +85c 5v 5% 24 720 edip ds1220ad-100+ 0c to +70c 5v 10% 24 720 edip ds1220ad-100ind+ - 40c to +85c 5v 10% 24 720 edip + denotes a lead (pb) - free/rohs - compliant package . package information for the latest package outline information and land patterns , go to www.maxim -ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regard less of rohs status. package type package code outline no. land pattern no. 24 e dip mdt24+1 ? 21-0245 downloaded from: http:///
ds1220ab/ad 8 of 8 revision history rev ision date description pages changed 121907 added package information table ; r emoved the dip mod ule package drawing and dimension table 9 10/10 updated the storage and soldering temperature information in the absolute maximum ratings section, removed the unused ac timing specs in the ac ele ctrical characteristics table, updated the ordering information table, updated the package information table 1, 3, 4, 7 downloaded from: http:///
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